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Computer Science & Engineering

Course Specification

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CSCE432, CSCE832 Course Specification

Catalog Description:

CSCE432 assumes knowledge of computer architecture, pipelining, memory hierarchy, instruction level parallelism, and compiler principles.
High performance computing at the processor level.  The underlying principles and micro-architectures of contemporary high-performance processors and systems.  State-of-the-art architectural approaches to exploiting instruction level parallelism for performance enhancements.  Case studies of actual systems highlight real-world trade-offs and theories.

Textbook(s) and/or Other Required Materials:

  1. John P. Shen and Mikko H. Lipasti, Modern Processor Design - Fundamentals of Superscalar Processors, McGraw-Hill Higher Education, 2005.
  2. John L. Hennessy and David A. Patterson, Computer Architecture -- A Quantitative Approach, 3rd Edition, Morgan Kaufmann Publishers Inc., 2003.

Prerequisites by Topic:

  1. Mastery of: the principles of classical single-processor Computer Architectures, including:
    1. Memory hierarchies, esp. Cache & main memory,
    2. Scalar processor architecture, RISC vs. CISC philosophies, & scalar pipeline performance.
  2. Familiarity with: Probability, & stochastic performance modeling of scalar processors, given standard stochastic & timing parameters (e.g. hit ratios, access times, cycle times, CPI, branch probabilities).

Course Objectives:

  1. Mastery of: the principles and practice of high-performance processor architectures, including: 
    1. Data parallelism vs. Instruction Level.Parallelism (ILP),
    2. Principles and practice of Vector processor architectures,
    3. Principles and practice of Superscalar Architectures.
    4. Principles and practice of Very Long Instruction Word (VLIW) Architectures

Topics Covered:

  1. Review of Scalar Processor Architecture Topics:
    1. Pipelining: concept, variations, performance,
    2. Scalar instruction pipelines: branching & load delays, ideal & expected performance,
    3. Superpipelining
    4. RISC vs. CISC philosophies.
  2. Vector Processors:
    1. Data Level Parallelism, regularity, predictability, chaining,
    2. Case studies: primarily the Cray family.
  3. Superscalar Processors:
    1. Instruction Level Parallelism,
    2. Branch processing and instruction flow techniques,
    3. In-order vs. out-of-order issue vs. out-of-order execution,
    4. Strong vs. weak consistency,
    5. Data dependencies and issue rules,
    6. Contemporary case studies.
  4. VLIW Processors:
    1. Concepts, HJP code scheduling: loop folding, trace scheduling, & percolation scheduling, b. Early case studies, e.g FPS AP-120B, Trace family, c. Contemporary case studies.

Relationship of Course to Program Objectives:

Contributes to Program Objective 4 through Program Outcome 4 by providing up-to-date information and depth of knowledge in the course topic.

Contribution of Coruse to Meeting the Professional Component:

Contributes to Criterion 4(b) by providing depth of knowledge in a specific engineering topic.

Class/Laboratory Schedule:

Lecture: 45 hours = 3 hours/week for 15 weeks